1. Field of the Invention
The present invention relates to an apparatus for to memory circuit testing, particularly to an apparatus for identifying state-dependent, defect-related leakage currents in memory circuits.
2. Description of the Prior Art
Conventional defect analysis techniques for memory circuits such as hot spot liquid crystal analysis or emission microscopy are performed on a single defective circuit. This can be done in a static mode by applying a DC voltage bias or in a dynamic mode while running a test pattern with varying addresses. These two methods can be combined with an operating current measurement. In general, these methods are not very efficient and accurate for the identification of defect related state dependent leakage currents. Hot spot liquid crystal analysis, emission microscopy, and a combination of both methods with an operating current measurement have the following disadvantages for the case of a single defective circuit under analysis. In the static mode, a defect might not cause any additional leakage contribution if the shorted circuit parts are on the same voltage level. In the dynamic mode, a defect can only be detected for certain critical addresses but there is no systematic way of identifying or triggering such critical addresses. Even adding an operating current measurement in parallel does not guarantee an accurate detection of critical addresses. The total operating current Itol(x,y) for a memory cell having address (x,y) is an overlay of the contribution Idef(x,y) of a defect and the contribution Icir(x,y) of all circuit elements. That is to say, Itol(x,y)=Idef(x,y)+Icir(x,y). However, both Idef(x,y) and Icir(x,y) are dependent on the address (x,y) and inseparable from the perspective of Itol(x,y).
Therefore, the object of the present invention is to provide a method and apparatus for memory circuit testing, which accurately identifies addresses of defective memory cells and detects leakage currents therein.
The present invention provides an apparatus for identifying state dependent defect related leakage currents in a tested circuit with a defect. The apparatus comprises a test system providing an input signal and an operating voltage, and a reference circuit the same as the tested circuit but without the defect receiving the input signal and the operating voltage, and operating at a first operating current, wherein, the tested circuit also receives the input signal and the operating voltage, and operates at a second operating current, and the test system senses a difference of the first and second operating current.
The present invention also provides an apparatus for identifying state dependent defect related leakage currents in a tested memory circuit with a defective cell. The apparatus comprises a test system providing an address signal and an operating voltage, and a reference memory circuit the same as the tested memory circuit but without the defective cell receiving the address signal and operating at a first operating current, wherein, the tested memory circuit also receives the address signal and the operating voltage, and operates at a second operating current, and the test system senses a difference of the first and second operating current.
The present invention further provides a computer-implemented method for identifying state dependent defect related leakage currents in a tested memory circuit with a tested cell using a reference memory circuit. The method comprises the steps of providing an address signal of the tested cell and an operating voltage to the reference and tested memory circuit so that the reference and tested memory circuit operate at a first and second operating current respectively, comparing the first and second operating current to obtain a difference of the first and second operating current; and deciding the tested cell as a defective cell when the difference is larger than a threshold value.